The present invention is related generally to extended range phase detectors and more specifically to an extended range phase detector with larger linear range having an output whose fundamental frequency is at least as high as the fundamental frequency of the input signals.
It is well known in the art that a phase detector with a linear characteristic over a phase range of 2.pi. can be easily realized with digital logic (see FIG. 1). The circuit here can be described as a one-stage bi-directional shift register whose output V.sub.d upon a rising edge on U, and a 0 upon a rising edge on D. This can also be described as an edge-sensitive R-S flip-flop. The phase detector characteristic V.sub.d is the average of the output of V.sub.d. The averaging serves to remove frequencies contained in V.sub.d that are also contained in U and D.
It is also well known in the art that the range of the Phase detector in FIG. 1 can be extended by preceding it with frequency dividers (see FIG. 2). Here the dividers cause the frequency of U to be one-third that of R and the frequency of D to be one-third that of V. As a result, the phase range is extended by a factor of 3 to 6.pi.. However, the output V.sub.d now contains frequencies that are one-third of those in R and V. This effectively triples the time required to produce V.sub.d and adversely restricts the response time of the phase detector.
Techniques are already known for extending the range of the phase detector in FIG. 1 without reducing the frequencies in V.sub.d. In Generalized Phase Comparators for Improved Phased-Locked Loop Acquisition, IEEE Transactions on Communication Technology, Volume COM-19, No. 6, pp. 145-148, December 1971, Oberest cites the n-stage "bi-directional shift register" (BSR) and the "asynchronous delay line" (ADL). In fact, he shows that these are equivalent. A three-state BSR is shown in FIG. 3a. The output V.sub.d is the sum of the signals V.sub.1, V.sub.2, V.sub.3. The effect of the inputs U and D on V.sub.1, V.sub.2, V.sub.3 is shown by the state diagram in FIG. 3b. Each rising edge of U causes another V to be 1, and each rising edge of D causes one less V to be a 1 (one more V to be a 0). If the BSR is in the 111 state, a rising edge of U causes no change; this is called a "cycle slip". If the BSR is in the 000 state, a phase change of 6.pi. corresponds to three more rising edges of U than of D. This advances the BSR to the 111 state, increasing V.sub.d by 3. The linear range can be extended further to 2n.pi. by using an n-stage BSR. However, there is a "problem of simultaneous input pulses" (Oberest, p. 1146 supra). If the rising edges of U and D are too close to each other, the effect of one edge will be lost, and the output of the phase detector becomes in error. Simple attempts at fixing this problem lead to "dead zones" or non-linearities in the characteristic.
The most general characterization of the function served by the BSR in FIG. 3a is an "up-down" counter. The count, in the case of the BSR, is represented by the number of V's that are l's. An example of another up-down counter is shown in FIG. 4a. Here the count is represented by the V's as a binary number (base-two number) To convert this count to an analog voltage V.sub.d, the V's must be weighted before summing: EQU V.sub.d =V.sub.1 +2V.sub.2 +. . . +2.sup.n-1 V.sub.n.
It may be noted that Oberest, in U.S. Pat. No. 3,723,889, extends the range of a phase detector and achieves a characteristic identical to that in FIG. 3c without "dead zones" or non-linearities. However, the frequency dividers (divide by N counters) he uses produce frequencies in V.sub.d that are lower than (1/N of) the frequencies in U and D.
Techniques are already known for realizing a 4.pi.-range phase detector with no dead zones. As described by Shahriary et al. in an article titled GaAs Monolithic Digital Phase-Frequency Discriminator, IEEE GaAs Symposium, pp. 183-186, 1985, such a circuit is shown in FIG. 5a. The state diagram in FIG. 5b shows the effect of the inputs R and V, and a simplified state diagram is shown in FIG. 5c. From this simplified state diagram, it can be seen that the circuit effectively realized a two-stage BSR (compare FIG. 3b). The circuit avoids the problem of simultaneous inputs by the existence of a fourth state 10. This is a momentary state that quickly reverts to state 01. Since states 10 and 01 both produce V.sub.d =1, the two states can be considered as one, as in FIG. 5c. The resulting phase detector characteristic with a linear range of 4.pi.is shown in FIG. 5d. However, there has heretofore been no way of extending the phase range of this circuit. It should be noted that FIG. 5a represents the device described in the Shahriary article using D flip-flops instead of the RS flip-flops described in Shahriary.
In my U.S. Pat. No. 4,587,496, I describe in FIG. 5 a proportional frequencY detector including an up-down counter 50, whose output is connected to an overflow and underflow multivibrator 56, 58 whose output is summed in summer 60. The multivibrators 56, 58 are connected so as to operate as slip cycle detectors. A two-state up-down counter is illustrated in FIG. 7 and a three-state up-down counter is illustrated in FIG. 9. In this context, the frequency detector is only concerned that slips are occuring and the direction. A delay insures that simultaneous inputs do not cause a slip to be missed, but as a result one slip causes multiple slips to be recorded. Thus, this circuitry was not considered for a phase detector which overcame the problems of the prior art.
Thus, it is an object of the present invention to provide an extended range phase detector whose output has a fundamental frequency at least as high as the fundamental frequency of its input signal.
Another object of the present invention is to provide a phase detector having a large linear range without dead zones and non-linearities.
A still even further object of the present invention is to indefinitely extend the range of a linear non-dead zone phase detector.
A still even further object of the present invention is to provide an extended range phase detector of an arbitrarily large linear range capable of handling simultaneously occurring input signals without error.
These and other objects are attained by using a three-state phase detector which is caPable of handling simultaneously occurring input signals accurately without dead zones or non-linearities and extending its range by using cycle slip detectors driving an up-down counter to extend the range of the three-state phase detector as cycle slips occur. The output of the three-state phase detector is combined with the output of the up-down counter to provide n+1 cycles of linear phase detection where n is the states of the up-down counter.
The three-state phase detector provides an output signal representing a lead state, a lag state and a center state. The three-state phase detector basically has a pair of outputs and a transition state. A pair of flip-flops receives respective input signals and provides one of a respective output signal. Logic is provided to reset the flip-flops when both of the flip-flops are in a set state simultaneously. This causes the appropriate transition state to occur, and only three stable states with four possible states are provided at the output of the three-state phase detector The two outputs of the phase detector are the Q and Q outputs respectively of the first and second flip-flops.
The cycle slip detector provides an up signal when the first input leads the second input by more than one cycle and a down signal when the first input lags the second input by more than one cycle. To accomplish this while accommodating simultaneous inputs, the cycle slip detector includes a lead circuit for providing the up signal when a first resulting change of the output signals of the three-state phase detector occurs after a predetermined time after the first input signal and a lag circuit for providing the down signal when a second resulting change of the output signals of the three-state phase detector occurs after the predetermined time after the second input signal. The lead and lag circuits of the cycle slip detector each include a timer initiated by a respective first or second input signal for providing a time-out signal after expiration of the predetermined time, an input flip-flop set by a respective first or second predetermined change of the output signal of the three-state phase detector and reset by the time-out signal, and an output flip-flop set by simultaneous occurrence of the time-out signal and a set signal from the input flip-flop and providing a respective up-down signal at its reset output.
The up-down counter may be an n-stage binary up-down counter with its outputs binarily weighted, or an n-stage bi-directional shift register. The output circuit includes digital-to-analog converters which convert the output of the up-down counter to an analog signal to be added with the digital-to-analog converted output of the three-state phase detector and an adder for adding the two analog signals.
Alternatively, a digital phase output can be produced by processsing the output of the three-state phase detector to provide a digital output representing the three states. The output of the up-down counter is provided to a digital adder which adds the most significant bit of the digital word form the three-state phase detector to the least significant bit of the output of the up-down counter. The total binary output has one less bit than the sum of the number of bits form the binary up-down counter and the digital output from the three-state phase detector.
Other objects, advantages and novel features of the present invention will become apParent from the following detailed description of the invention when considered in conjunction with the accompanying drawings